A Microthreaded Chip Multiprocessor with a Vector instruction Set

This paper describes a microthreaded, multiprocessor and presents simulations from a single processor implementation. The microthreaded approach obtains threads from a single context and exploits both vector and instruction level parallelism (ILP). Threaded code can be generated from sequential code, where loops may be transformed into families of, possibly dependent, concurrent threads. Instruction fetch and issue are controlled by statically labelling instructions for vertical or horizontal transfer, depending on whether a potential data or control dependency exists. Horizontal transfer is the deterministic component of conventional next instruction processing (increment PC or unconditional branch). Vertical transfer is a context switch, which executes the next instruction from a ready thread. This allows non-determinism in data access (cache miss or signalling between concurrent threads) and in control (all conditional branches are labelled vertical). The paper will outline the microarchitecture, the thread creation mechanism based on a vector instruction set and the synchronisation techniques used. It describes a novel approach to dynamic register allocation that supports regular dependencies between families of threads. We present simulation results for a simple 5-stage pipeline, using a three level memory hierarchy. We have measured the influence of two parameters, cache delay and number of registers. The results show that the microthreaded performance is significantly superior to the conventional pipeline on which it is based. We show that the microthreaded pipeline can achieves an IPC of 0.8, even in the presence of a 1000 cycle L2-cache miss penalty.